1. Field of the Invention
The invention relates to an address generating circuit for data compression for fetching data stored in a failure analysis memory to a CPU at high speed and an arbitrary compression rate.
2. Prior Art
A multi-function and high speed of a failure analysis of a memory tester have been recently required as a memory device has a large capacity. As a hardware to meet the requirement, there is employed an address generating circuit for data compression data for fetching data stored in a failure analysis memory to a CPU at high speed and an arbitrary compression rate.
As a conventional address generating circuit for data compression, there is illustrated, for example in FIG. 3, wherein increment addresses are generated to reduce processing time for fetching data stored in a failure analysis memory to a CPU.
In the address generating circuit 1 for data compression shown in FIG. 3, a comparator 1A compares an end address data or signal a which is inputted from an external device to an input terminal A thereof with an address data I which is generated in an up counter 4A and inputted to an input terminal B thereof, wherein the comparator 1A outputs an address end signal k if the address data I is greater than the end address data a.
The selector 2A alternatively selects a start address data b which is inputted thereto an external device, and an addition data which is calculated by an adder 6A and inputted thereto in response to an address load cell signal c which is inputted thereto from an external device, and it outputs the selected data to the flip flop 3A. The flip flop 3A holds the inputted selected data at a timing of a clock signal which is generated by executing a logical AND operation between an address load enable signal d and a clock signal Ae which are respectively inputted to an AND gate 5A from the external device. The selected data held by the flip flop 3A becomes an input data of the up counter 4A, in which the input data is incremented by the up counter 4A to output the address data I.
In an adder 6A, an address compression signal h which is inputted thereto from the external device and the data outputted from the flip flop 3A are added, and the added data is outputted to the selector 2A. A down counter 7A receives the address compression signal h as input data and outputs an address carry signal m when the output data thereof is "1". Both the up counter 4A and the down counter 7A are controlled in counting operation by an address load signal i which is inputted thereto through a flip flop 10A and a clock enable signal j through a flip flop 11A.
That is, the address generating circuit 1 for data compression specifies an X coordinate as an X address and a Y coordinate as a Y address to generate address data for specifying to access to the failure analysis memory provided that the failure analysis memory includes memory areas which can be specified by addressed based on a two-dimensional coordinate system (X coordinate, Y coordinate). The address generating circuit 1 requires two address generating circuits for data compression having the same construction for specifying the X address and the Y address.
The operation of the address generating circuit 1 shown in FIG. 3 is explained with reference to FIG. 4. The X address generating circuit for data compression and the Y address generating circuit for data compression normally perform address generating operations relative to a blocks for an X address compression rate a and Y address compression rate b which are prepared by partitioning memory areas of a failure analysis memory shown in FIG. 4 (data in the block is compressed to form one bit compression data, hereinafter refereed to as address compression blocks). In the address compression blocks of FIG. 4, address data which are generated in the Y address generating circuit for data compression and the Y address generating circuit for data compression respectively generate addresses for incrementing the addresses in the direction of X while an X start address XB and a Y start address YB serve as a start address at the X address compression rate a and the Y address compression rate b.
That is, in the address generating circuit 1 for data compression shown in FIG. 3, the operation of generating the X start address is performed in the sequence of (1).fwdarw.(2).fwdarw.(3) . . . in the address compression blocks of FIG. 4, wherein the number of addresses to be incremented at the X address compression rates a and b is set.
However, there occurs a problem in the conventional address generating circuit 1 for data compression shown in FIG. 3 that a start address is not generated in accordance with inherent address compression blocks shown in FIG. 4 if the start address is generated from an arbitrary point of the address compression blocks, since the start address is always generated as a leading address in the address compression blocks.
That is, there occurs a problem that if the address is incremented from the X start address XB and the Y start address YB which are set at the position (1) to the position (2) at the same address compression rate a as shown in FIG. 4, the access position moves to the next address compression block, making it difficult to normally perform the operation for compressing and specifying the address in the address blocks which are repaired by partitioning the memory areas of the failure analysis memory since the number of addresses is incremented from the start address generated at an arbitrary point without changing the address compression rate.
Further, there also occurs another problem in the address generating circuit 1 for data compression shown in FIG. 3 that it can not be operated with a single clock since the flip flop 3A and the up counter 4A for holding the start address are connected to each other by a pipe line.
That is, since a clock for setting a timing of the holding operation of the flip flop 3A is a clock signal Ae, and a clock for setting a timing of the counting operation of the up counter 4A is a clock signal Bg, requiring two kind of clock signals, resulting in generation of a problem of applying a load in constructing the circuit.